1. Technical Field
This disclosure relates to a recessed gate structure and a method of forming the same. This disclosure also relates to a semiconductor device having such a recessed gate structure and to a method of manufacturing the same.
2. Description of the Related Art
As integration within semiconductor devices becomes more highly integrated, line widths and line intervals of patterns on semiconductor substrates have decreased resulting in increasingly fine patterns. Thus, techniques have evolved to accurately and precisely form fine patterns on substrates. One such technique involves the formation of recessed electrodes that occupy minimal area on the substrate and have sufficient effective channel length. Such recessed electrodes have been used as gate electrodes of semiconductor devices. Exemplary semiconductor devices incorporating recessed gate electrodes have been disclosed in Korean Patent No. 304,717, U.S. Pat. No. 6,762,098, and Japanese Patent Laid-Open Publication No. 2000-349289.
Generally, recessed gate electrodes are formed by creating a recess within a substrate and filling the recess with conductive material. The recess typically includes an upper portion and a lower portion that has a larger maximum diameter than the upper portion. Accordingly, the upper portion of the recess can become clogged with the conductive material before the recess itself is completely filled. As a result, a void is often defined within a central region of the conductive material present in the lower portion of the recess.
Metal-oxide semiconductor (MOS) transistors incorporating recessed gate electrodes are generally not adversely influenced by voids centrally located within the lower portion of a recess. However, voids of recessed gate electrodes can migrate easily due to silicon diffusion facilitated during subsequent processes. When such voids migrate, electrical characteristics of the MOS transistors can deteriorate.
FIG. 1 illustrates a cross-sectional view of a recessed gate electrode having a void that has migrated from a central region of conductive material present in the lower portion of a recess to a peripheral region thereof.
Referring to FIG. 1, a recess is formed in a substrate 10, a gate oxide layer 12 is formed over the top surface of the substrate 10 and along inner surfaces of a recess formed in the substrate 10 and conductive material 16 (i.e., the recessed gate electrode) is formed over the gate oxide layer 12 and into the recess. Due to the internal geometry of the recess, the upper portion of the recess becomes clogged, leaving a void 14 defined within a central region of the conductive material in the lower portion of the recess. During subsequent processes, the void 14 can migrate from the central region to a peripheral portion thereof (as shown in the figure) and contact a gate oxide layer 12. When the void 14 contacts the gate oxide layer 12, a leakage current is generated while a threshold voltage of the MOS transistor deviates from a preset value and irregularly fluctuates. The existence of such leakage current and threshold voltage fluctuation deteriorate the electrical characteristics of any MOS transistor that is subsequently formed using the recessed gate electrode.